Hardware Engineers: RTL Implementation and Evaluation Workflows
Terac · Remote · US only
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First recorded by Psst: 1 November 2026. Sign in with Google to continue to the employer. A free account is enough.
The 20-second read
- Experience
- Experience not stated
- Where you can live
- US only
- Skills and tools
- react
- Job type
- Contract or freelance
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Job details
- Where you can work
- United States
- Employment type
- Contract
- Advertised pay
- $147/hr
- Experience
- Experience not stated
- Employer publication date
- 31 October 2026
- First recorded by Psst
- 1 November 2026
- Last checked at the source
- 2 November 2026
About the job
WHAT WE'RE RESEARCHING
We're running a paid study on modern hardware description workflows and RTL implementation. Our goal is to understand how engineers approach automated evaluation and design verification in complex systems. This research feeds directly into improving tooling and methodologies for hardware development.
HOW IT WORKS
You will participate in a remote interview to walk us through your typical hardware design process. We will ask you to review specific RTL implementation scenarios and discuss your approach to automated evaluation. You will share your screen to demonstrate how you handle hardware description workflows in practice. The session concludes with a discussion on the challenges you face with current verification tools.
WHO THIS IS FOR
We are looking for experienced hardware engineers who specialize in RTL design and implementation. We welcome ASIC designers, FPGA engineers, hardware verification specialists, and system-on-chip (SoC) architects. You should have hands-on experience with hardware description languages and automated evaluation frameworks.
WHAT YOU'LL DO
- Walk us through your approach to RTL implementation and hardware description
- Review and react to specific automated evaluation scenarios
- Describe a recent time you tackled a complex hardware verification challenge
- Provide feedback on current workflows and tooling gaps
WHO SHOULD APPLY
- Professional experience in hardware engineering or RTL design
- Hands-on background with hardware description languages (Verilog, VHDL, or SystemVerilog)
- Familiarity with automated evaluation and verification workflows
- Comfortable discussing technical design choices in a remote interview
COMPENSATION
$147 per hour
READY TO PARTICIPATE?
Start your paid interview now https://terac.com/interview/start/r/69475ab4-cbfc-48d3-9cc3-61e9840201b9?utm_source=ashby_listing_description
ABOUT TERAC
Terac is building the world's largest pool of vetted human experts for AI. Researchers, AI labs, and product teams use Terac to recruit, screen, and pay study participants across industries, languages, and skill sets.
Learn more at terac.com https://terac.com or on YouTube at @jointerac https://www.youtube.com/@jointerac.
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